1. Field of the Invention
The present invention relates generally to an apparatus of and a method for executing a subprogram, and more particularly, to an apparatus of and a method for executing a subroutine and an interrupt processing program in a system having a program memory comprising two or more memory banks.
2. Description of the Background Art
A program is required in order to cause a data processing system to perform a predetermined data processing operation. Therefore, an ordinary data processing system comprises, as its most simplified manner, a main memory for storing various data, a user program applied from an external apparatus, or the like, a program memory for fixedly storing a program inherent in this processing system, or the like, and a central processing unit (CPU) for performing data processing in accordance with the programs.
However, as the data processing system is made to perform a multi-function, the scale of each of the processing programs is enlarged, so that a memory area for storing the processing programs is increased. In this case, since memory capacity of the CPU is defined by the number of address bits which can be utilized by the CPU, the large-scale processing programs cannot be all stored in the memory area. In order to deal with this, a memory bank switching scheme has been put into practice in which a plurality of memory banks are provided and the memory banks are switched so that a memory area in the CPU is extended. On this occasion, different processing programs are stored in the respective memory banks. Switching of the memory banks is generally performed in accordance wit a control program exclusively used for bank switching stored in a common area of a main memory provided separated from the memory banks.
However, in a relatively small capacity system in which restrictions are imposed on a program are from the viewpoint of its memory capacity and such a common area cannot be provided in a main memory, it is necessary to cause processing programs in memory banks to control bank switching. Japanese Patent Laying-Open Gazette No. 120543/1987 discloses an example of such bank switching. Referring now to FIG. 1, description is made on a conventional bank switching method disclosed in this gazette.
Referring to FIG. 1, it is assumed that each of banks A and B has addresses 0000H to FFFFH, and a memory area having addresses 0000H to 1FFFH is assigned for programs. In addition, it is assumed that this data processing system is a system of a pre-fetch scheme of fetching the next instruction during the execution of an instruction.
First, the bank A is accessed by the CPU, so that steps (instructions) of the programs stored therein are sequentially read out and executed. When the program advances to an address x so that an instruction of bank switching stored thereat is read out and executed, a memory bank to be accessed is switched from the bank A to the bank B. This bank switching is performed by an additional bit to an address. More specifically, a combination of this additional bit and a counted value of an address counter (program counter) for addressing becomes a bank address. For example, an additional bit for the bank A is "0", and an additional bit for the bank B is "1". The bank A is accessed in the case of addresses 00000 to 0FFFF, while the bank B is accessed in the case of addresses 10000 to 1FFFF.
In this bank switching scheme, an additional bit (stored in a suitable position of a memory, practically in an extended address register) is updated by the instruction of bank switching, so that bank switching is achieved. However, a program counter is not changed in the count value. Thus, a memory access address outputted by the program counter becomes an address x, x+1, x+2 . . . . Therefore, in the bank B, program instructions stored in the address x+2 and subsequent addresses in the bank B are sequentially executed. Meanwhile, since a system of a pre-fetch scheme is here assumed, an instruction of bank switching read out by accessing to the address x in the bank A is executed at timing at which the next address x+1 is accessed, so that bank switching is achieved. On this occasion, since an instruction read out at the address x+1 is an instruction in the bank A and is not required, an instruction "NOP" (no operation) is stored at the address x+1 in the bank A. As a result, no instruction is executed at timing at which the address x+2 is accessed, and an instruction from the address x+2 (represented by the hatched portion in FIG. 1) in the bank B is only read out. When the address x+3 is accessed, an instruction at the address x+2 in the bank B is executed.
Thus, if this bank switching scheme is applied to the execution of a subroutine, the following problems occur. Conventionally, a program technique of storing a program repeatedly used in separate memory area as a subroutine and calling this subroutine as needed has been known, in order to avoid the redundancy of a program and efficiently utilize a program area. Let us consider a case in which a subroutine in one memory bank is called from a main routine in the other memory bank and executed, in the above described bank switching scheme. In this case, in a plurality of portions where a main routine attempts to call a subroutine, address matching of a bank switching address of the main routine and a first address of the subroutine is required, so that a considerable amount of time and effort is required to develop a program. Therefore, the efficiency of this system is poor.
Additionally, if and when the number of subroutines to be called is large (there are many types of subroutines), the restriction that address matching is required brings about a situation where a program which is a desired end cannot be developed. In addition, considering a case in which three or more memory banks are provided, if the above described bank switching scheme is applied, the same difficulty arises, so that it is almost impossible to, for example, nest the subroutines.
In order to overcome such a difficulty, it is necessary to store all the subroutines as required in each of the memory banks. However, in this case, memory capacity required in each of the memory banks is increased, so that all desired programs cannot be stored in a limited program memory area.
Additionally, a processing program similar to a subroutine includes an interrupt processing routine. This interrupt processing routine is similar to the subroutine in that it is an independent program stored in a memory area other than an area for the main routine, while being entirely different from the subroutine in that it is not related to the content of processing of the main routine. In the following description, the subroutine and the interrupt processing routine are generically referred to as a subprogram in the sense that they are a separate program from the main routine.
An interrupt control method in the memory bank switching scheme is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 30050/1982. In this prior art document, an interrupt processing program or a bank control program for interruption for designating a particular memory bank storing the interrupt processing program, a bank address or the like are stored in a common memory area provided separately from a plurality of memory banks. Interrupt processing is performed in accordance with a processing program stored in this common memory area and/or a particular memory bank.
This prior art scheme cannot be applied to a system in which a region for storing a program associated with interrupt processing cannot be provided in a common memory area provided separately from memory banks, on a designing view of a system or depending on memory capacity of the system. Thus, in such a system, the same interrupt processing program is forced to be stored in each of the memory banks. This causes the interrupt processing program to unnecessarily occupy a memory area extended by the memory bank switching scheme, so that a memory area for storing a desired processing program becomes narrow.
Additionally, the above described Japanese Patent Laying-Open Gazette No. 120543/1987 has proposed a method for designating a jump address using an instruction JMP (jump) in place of an instruction NOP subsequent to an instruction of bank switching to eliminate the necessity of address matching in the memory bank switching scheme. However, in this prior art method, the jump address is designated only using the instruction JMP after bank switching step, and designation of a return address or the like is not considered at all. In addition, in a general CPU, it is not ensured that actual switching of memory banks is completed after the execution of the instruction JMP. Thus, this method makes it difficult to perform a reliable operation. Thus, this prior art method cannot be applied to a subroutine executing method and an interrupt processing method in a system of a memory bank switching scheme.